SystemVerilog enhances hardware modeling through higher-level abstractions like enumerated types, 2-state data types, and specialized procedural blocks such as always_comb, always_ff, and always_latch. These constructs simplify the design and verification of finite state machines (FSMs) while improving consistency across simulation and synthesis tools.

Enumerated Types for FSM States

Enumerated types restrict variables to a predefined set of symbolic values, enabling clearer and more maintainable FSM descriptions. For example, a traffic light controller can define states as:

enum {RED, GREEN, YELLOW} current_state, next_state;

However, using the default base type (int) may lead to mismatches between RTL simulation and gate-level behavior. A better approach explicitly defines the encoding and uses a 4-state base type like logic:

enum logic [2:0] {
    RED    = 3'b001,
    GREEN  = 3'b010,
    YELLOW = 3'b100
} current_state, next_state;

This ensures synthesis preserves the intended encoding and improves debuggability by initializing to 'X instead of 0.

One-Hot Encoding with Reversed Case Statements

For one-hot FSMs, reversed case statements can improve synthesis efficiency. Instead of matching the full state vector, the case expression is 1'b1, and each case item checks a single bit:

enum {R_IDX = 0, G_IDX = 1, Y_IDX = 2} state_index;
enum logic [2:0] {
    RED    = 3'b001 << R_IDX,
    GREEN  = 3'b001 << G_IDX,
    YELLOW = 3'b001 << Y_IDX
} current_state, next_state;

always_comb begin
    next_state = current_state;
    unique case (1'b1)
        current_state[R_IDX]: if (sensor) next_state = GREEN;
        current_state[G_IDX]: if (green_timer == 0) next_state = YELLOW;
        current_state[Y_IDX]: if (yellow_timer == 0) next_state = RED;
    endcase
end

This technique links bit positions to symbolic names via shift operations, reducing the risk of encoding mismatches.

Unique Case for Safety and Optimization

The unique keyword enforces that exactly one case branch matches during execution. It provides three benefits:

1. Enables parallel evaluation (similar to parallel_case).
2. Detects overlapping conditions at runtime.
3. Ensures all possible values are covered (like full_case), issuing warnings for uncovered or ambiguous cases.

When combined with enumerated types, unique case eliminates the need for explicit default branches assigning 'X, since only valid enumerated values are possible.

Safe Assignment Practices

Enumerated variables must be assigned only from their defined label set. Direct bit assignments or literal values (e.g., next_state = 3'b000) are illegal and can introduce invalid states. Instead, always assign full symbolic values:

// Correct
next_state = GREEN;

// Incorrect
next_state[G_IDX] = 1'b1; // Avoid bit-select assignments

Type Casting and Enum Methods

Arithmetic on enum variables produces the base type (e.g., int), which cannot be directly assigned back. Use casting or built-in methods:

typedef enum {IDLE, RUN, DONE} fsm_state_t;
fsm_state_t state, next;

// Static cast (no bounds check)
next = fsm_state_t'(state + 1);

// Dynamic cast (runtime check)
$cast(next, state + 1);

// Enum method (safe increment)
next = state.next();

Dynamic casting and enum methods prevent out-of-range assignments, aiding robustness.

Reset Behavior and Initialization

Using 2-state types (e.g., bit) initializes variables to 0, masking missing or faulty reset logic. In contrast, 4-state types (logic) initialize to 'X, exposnig unreset registers during simulation.

An FSM using default enum values may appear functional at startup even without reset, because the initial 0 matches the first enum label. To avoid this:

• Use logic as the base type to get 'X initialization.
• Replace always @(state) with always_comb, which executes once at time zero, ensuring correct initial decoding.

Combining always_comb, unique case, and 4-state enums creates self-checking, synthesizable FSMs that behave consistently from RTL to gate level.