When selecting a Process Design Kit (PDK) for educational purposes, open-source alternatives are often preferred to avoid licensing and copyright restrictions associated with foundry-provided kits. Among the options evaluated—such as Synopsys’ SAED28_32nm, Cadence’s GPDK45nm, and several open PDKs—the ASAP7nm PDK stands out as a strong candidate despite some limitations.

Commercial teaching PDKs like SAED and GPDK offer comprehensive libraries including standard cells, I/Os, memory compilers, and PLLs. However, they are tightly coupled to their respective vendor tools: SAED requires Synopsys Custom Compiler and IC Validator, while GPDK relies on Cadence Virtuoso with Assura for DRC/LVS—neither supports industry-standard signoff tools like Calibre. In contrast, ASAP7 provides Calibre-compatible DRC/LVS decks and Virtuoso-readable analog views, aligning more closely with real-world design flows.

The intended teaching flow is: VCS & Verdi (front-end) → Design Compiler (synthesis) → Innovus (place-and-route) → PrimeTime (timing signoff) → Calibre (physical signoff). ASAP7 fits this ecosystem well, especially given its 7nm FinFET technology node—a rarity in academic settings but highly relevant for preparing students for advanced semiconductor design challenges in China and globally.

PDK Structure

The ASAP7nm repository includes:

• asap7_pdk_r1p7: Analog PDK
• asap7sc6t_26 and asap7sc7p5t_28: Digital standard cell libraries (6-track and 7.5-track)
• asap7_sram_0p0: SRAM macros

Analog PDK Setup and Limitations

To use the analog PDK in Cadence Virtuoso:

1. Edit set_pdk_path.csh to point PDK_DIR to the installation path.
2. Run set_pdk_path.csh and setup_asap7.csh.
3. Add asap7_TechLib and asap7ssc7p5t via cdslib definitions.

The analog library includes only basic FinFET devices (LVT, RVT, SLVT, SRAM variants) without resistors, capacitors, diodes, or layout views. Only HSPICE model are provided—no Spectre support. While sufficient for viewing and minor layout edits, it lacks completeness for full analog design. The display rules (display.drf) must be manually merged in Virtuoso to render layers correctly. The process uses 1P9M (10 metal layers inccluding PAD).

SRAM Library

The asap7_sram_0p0 directory contains pre-generated SRAM macros but no memory compiler. It includes:

• GDS examples (32b, 64b, 128b port widths)
• Behavioral Verilog models (e.g., 64-bit width, 1024 depth)
• Generated LEF, LIB, and Verilog files for 36 configurations (widths: 16–80 in steps of 2; depths: 256, 512, 1024)

Namming convention example: srambank_128x4x16 implies depth = 128 × 4 = 512, width = 16 bits. A simple Python script can extract matching files by user-specified width and depth:

import os
import shutil

def extract_sram_files(width, depth, base_dir="../generated"):
    target_depth = int(depth) // 4
    dest = f"sram_{width}x{depth}"
    found = False

    for fmt in ["LEF", "LIB", "verilog"]:
        src_dir = os.path.join(base_dir, fmt)
        if not os.path.exists(src_dir):
            continue
        for f in os.listdir(src_dir):
            if str(width) in f and str(target_depth) in f:
                if not found:
                    os.makedirs(dest, exist_ok=True)
                    found = True
                subdir = os.path.join(dest, fmt)
                os.makedirs(subdir, exist_ok=True)
                shutil.copy(os.path.join(src_dir, f), subdir)

    if not found:
        print("Error: No matching SRAM files found.")

# Usage
w = input("Width: ")
d = input("Depth: ")
extract_sram_files(w, d)

Note: GDS and CDL netlists are missing from the generated set, so physical verification (DRC/LVS) isn’t possible for custom SRAM instances. Layout inspection using provided GDS files (e.g., srambank_32b.gds) reveals compact cells (~0.057 µm²), significantly smaller than 28nm counterparts (~0.414 µm²).

Digital Standard Cell Libraries

Both 6T and 7.5T libraries include:

• Verilog RTL
• GDS layouts
• LEF abstracts
• NLDM and CCS timing libraries (SS/TT/FF corners)
• QRC extraction data
• Datasheets and tech LEF

Four threshold variants per cell: SLVT (~0.05V), LVT (~0.125V), RVT (~0.2V), and SRAM-specific (NMOS ~0.275V, PMOS ~0.225V). Cell types include logic gates (SIMPLE), flip-flops (SEQ), buffers/inverters (INVBUF), AO/OA compound gates—covering typical digital design needs. The 6T library additionally includes clock inverters (CKINVDC).

While the digital flow is robust, the absence of I/O pads, PLLs, and a true memory compiler limits full-chip implementation. However, these gaps can be addressed incrementally for educational projects.