An Instruction Set Architecture (ISA) defines the interface between a computer’s hardware and its software, specifying the supported data types, registers, memory addressing modes, and the set of instructions that a processor can execute. The equivalence of hardware and software means that the same computational function can be realized through different physical implementations, a principle that underpins modern system design.

A typical computer comprises three fundamental components: a processor that interprets and executes programs, memory for storing data and instructions, and a mechanism for transferring data to and from the external environment. Clock frequency is commonly measured in MHz (or GHz for modern systems). Two basic memory categories are Random Access Memory (RAM)—volatile, readable and writable—and Read-Only Memory (ROM)—non‑volatile, primarily readable, and suited for storing fixed code and constant data.

Integrated circuit technology advanced through several generations: SSI (Small Scale Integration, 10–100 components per chip), MSI (100–1,000 components), LSI (1,000–10,000 components), and VLSI (over 10,000 components), which inaugurated the fourth generation of computers.

The von Neumann architecture introduced the stored‑program concept, using a memory device (originally mercury delay lines) to hold both instructions and data. This replaced earlier hard‑wired programming and established the layered machine organization that remains foundational today. Execution follows a repeating Fetch–Decode–Execute cycle: the processor fetches an instruction from main memory, decodes the operation code, and then executes the specified operation.

CPU Organization and the MARIE Model

The central processor’s duty is to retrieve instructions, decode them, and perform the required operations on data in the correct sequence. The Arithmetic Logic Unit (ALU) handles arithmetic and logic operations, while the Control Unit supervises instruction execution and data movement, basing its decisions on the program counter and status registers.

Buses are shared collections of wires that connect subsystems. A master initiates a transfer; a slave responds. Data buses carry information, control lines manage access and purpose, and address lines indicate data location. A bus cycle is the clock interval required for a complete transfer. Four common arbitration methods resolve bus access conflicts:

• Daisy chain: a single grant line passes from highest to lowest priority device.
• Cantralized parallel: each device has a request line, and a separate arbiter selects who may use the bus.
• Distributed self‑selection: devices independently decide which has the highest priority.
• Distributed collision‑detection: any device may request the bus; if simultaneous requests are detected, devices retry.

Clock cycles are the basic timing units. CPU time for a program can be expressed as:

$$\text{CPU time} = \frac{\text{Instructions}}{\text{Program}} \times \frac{\text{Average cycles}}{\text{Instruction}} \times \frac{\text{Seconds}}{\text{Cycle}}$$

Memory can be organized by byte addressing (each byte has a unique address) or word addressing (each word has an address). In low‑order interleaving, the low‑order address bits select the memory module; in high‑order interleaving, the high‑order bits are used.

Interrupts alter the normal flow of execution. They may be maskable (can be disabled) or non‑maskable (must be serviced), and can occur within or between instructions.

The MARIE architecture contains seven registers:

• AC – Accumulator, holds data for ALU operations.
• MAR – Memory Address Register, stores the address of a memory reference.
• MBR – Memory Buffer Register, holds data just read from or to be written to memory.
• PC – Program Counter, points to the next instruction.
• IR – Instruction Register, holds the instruction current being decoded.
• InREG – Input Register, receives data from input devices.
• OutREG – Output Register, holds data for output devices.

Register Transfer Language (RTL) describes micro‑operations on registers. An assembler processing symbolic code typically makes two passes: the first builds a symbol table, and the second generates machine code by resolving labels.

A datapath is a network of storage units and the ALU, connected by buses and coordinated by a clock. During the fetch–decode–execute cycle, the following micro‑operations occur:

MAR ← PC
IR ← M[MAR], PC ← PC + 1
MAR ← IR[11–0], decode IR[15–12]
MBR ← M[MAR] ; then execute the actual instruction

Interrupt‑driven I/O works as follows: the CPU notifies an I/O device to start an operation, then continues other tasks. When the device is ready, it sends an interrupt request. The CPU acknowledges the interrupt, services it, and then resumes the normal fetch–decode–execute cycle.

Instruction Set Architecture

Instruction sets are characterized by where operands are stored (stack, accumulator, registers, or memory), the number of explicit operands (0, 1, 2, or 3), operand location, operation types, and operand sizes.

Instruction length involves trade‑offs: fixed‑length instructions are easier to decode and beneficial for pipelining, though they may waste memory; variable‑length enstructions save space but complicate decoding. Designs often use two or three lengths as a compromise. Expanding opcodes provide a flexible scheme: short opcodes are available, but longer ones can be used when more operands or addressing modes are needed.

Endianness specifies byte ordering. Big‑endian places the most significant byte at the lowest address; little‑endian places the least significant byte at the lowest address. Little‑endian machines can simplify high‑precision arithmetic; big‑endian tends to be more human‑readable in hexadecimal dumps.

Addressing modes determine how an operand’s effective address is computed:

• Immediate: the operand is part of the instruction.
• Direct: the instruction contains a memory address.
• Register: a register number specifies the operand.
• Indirect: the address field points to a memory word that holds the effective address.
• Register indirect: a register holds a pointer to the operand.
• Indexed: an index register’s value is added to a base address to form the effective address.
• Based: a base register plus an offset yields the address.
• Stack: operands are implicitly on a stack.
• Based‑offset / based‑indexed: combines a base register displacement with an index.

Pipelining is an instruction‑level parallelism technique that overlaps the execution of multiple instructions. Each stage completes a part of the fetch–decode–execute cycle. For a pipeline with k stages, executing n instructions with a cycle time t and a non‑pipelined execution time t_seq per instruction, the speedup is:

$$S = \frac{n \cdot t_{\text{seq}}}{(k + n - 1) \cdot t_{\text{pipe}}}$$

In the ideal case with a large number of instructions, the theoretical speedup approaches k.

Memory Hierarchy

The memory hierarchy exploits locality of reference to bridge speed and capacity gaps. Temporal locality means recently accessed data is likely to be accessed again soon; spatial locality means nearby addresses tend to be accessed together; sequential locality refers to the tendency of instruction streams to be accessed in order.

SRAM is faster, more expensive, and less dense than DRAM, which requires periodic refresh. ROM retains data permanently.

A cache holds a subset of main memory contents. The Effective Access Time (EAT) combines hit time, miss penalty, and hit rate H:

$$EAT = H \cdot T_{\text{cache}} + (1 - H) \cdot T_{\text{mm}}$$

Cache mapping strategies dictate where a block may reside:

• Direct mapped: a block can go into exactly one cache line.
• Fully associative: a block can be placed in any line.
• Set associative: a compromise where a block maps to a set of lines.

The three address fields for direct mapped caches are tag, block, and word. The block field selects a specific cache line; the tag field identifies which main memory block is currently stored there; the word field locates the desired word within the block. For set‑associative caches, the fields are tag, set, and word.

Write policies include:

• Write‑through: updates both cache and main memory immediately.
• Write‑back: writes to main memory only when a dirty cache block is evicted. A dirty block is one that has been modified.

Virtual memory extends the apparent memory space using disk storage. A Translation Look‑aside Buffer (TLB) caches page table entries to speed address translation.

I/O and Storage Systems

Amdahl’s Law quantifies overall system speedup S when only part of a system is improved:

$$S = \frac{1}{(1 - f) + \frac{f}{k}}$$

where f is the fraction of execution time affected by the improvement and k is the speedup of that part.

I/O control techniques vary in CPU involvement:

• Programmed I/O (polling): the CPU continuously checks status registers of each I/O device. It is simple but wastes CPU cycles, making it suitable for dedicated embedded systems.
• Interrupt‑driven I/O: devices signal the CPU when they are ready. This avoids constant polling and is common in general‑purpose personal systems.
• Direct Memory Access (DMA): a DMA controller takes over data transfers between memory and I/O devices. The CPU initiates the transfer and resumes other work; the DMA controller signals completion via an interrupt. It is used in small to medium systems. DMA must steal memory cycles from the CPU.
• Channel I/O: dedicated I/O processors manage multiple I/O paths. Slow devices can be multiplexed onto a single channel. This architecture suits high‑throughput transaction processing.

Disk performance is characterized by seek time (positioning the read/write head over the correct track) and rotational latency (waiting for the desired sector to spin under the head). Their sum is the access time.

RAID (Redundant Array of Independent Disks) improves performance and/or reliability:

• RAID 0 (striping): distributes data blocks across disks with no redundancy. It offers the highest write performance but no fault tolerance.
• RAID 1 (mirroring): duplicates all data on a second disk set, providing excellent fault tolerance at the cost of doubled storage.
• RAID 2 (bit‑level striping with Hamming code): rarely used in practice; error‑correction codes are generated per bit stripe.
• RAID 3 (bit‑interleaved parity): stripes data at the bit level and uses a dedicated parity disk (XOR).
• RAID 4 (block‑level parity): larger stripes with a dedicated parity disk; suffers from a write bottleneck on the parity disk.
• RAID 5 (distributed parity): stripes data and distributes parity across all disks. It provides cost‑effective redundancy and good read throughput, widely adopted in commercial systems.
• RAID 6 (dual parity): uses two independent parity blocks to tolerate two simultaneous disk failures.

Alternative Architectures

CISC processors rely on microcode to implement complex instructions, while RISC architectures use hardwired control to complete most instructions in a single clock cycle. RISC designs typically have shorter cycle times and a larger number of registers, leading to faster overall execution despite a potentially higher instruction count.

Flynn’s taxonomy categorizes architectures by the number of instruction and data streams:

• SISD – Single Instruction, Single Data (traditional uniprocessor).
• SIMD – Single Instruction, Multiple Data (vector processors).
• MISD – Multiple Instruction, Single Data (rare).
• MIMD – Multiple Instruction, Multiple Data (modern multicores).

VLIW (Very Long Instruction Word) processors bundle multiple independent operations into a single wide instruction, relying on the compiler to schedule parallelism statically. Other non‑traditional models include dataflow computing, neural networks, and systolic arrays.

Performance bottlenecks are often categorized by the limiting resource: memory‑bound, CPU‑bound, or I/O‑bound.