DesignWare Building Block IP Overview

DesignWare Building Block IP (DWBB), also referred to as the Foundation Library, is a collection of pre-optimized, reusable intellectual property blocks tightly integrated into the Synopsys synthesis environment. DWBB enables transparent and high-level performance optimization during synthesis operations. This library contains numerous components designed to accelerate design reuse and boost productivity significantly.

The library encompasses several categories:

• Base Library: IP components bound to HDL compilers that implement common arithmetic and logical operations
• Logic: Combinational and sequential IP blocks
• Mathematics: Arithmetic and trigonometric IP blocks
• Digital Signal Processing: FIR and IIR filters
• Memory: Registers, FIFOs and FIFO controllers, synchronous and asynchronous RAM, stacks
• Interfaces: Cross-clock domain components
• Specialized: Data integrity, interfaces, JTAG IP, and more

DWBB leverages highly automated design reuse mechanisms, allowing Synopsys synthesis tools to transparently execute various high-level optimizations.

When using HDL addition operators like "+", the HDL compiler infers that an adder resource is required and inserts an abstract representation into the circuit netlist. This abstract representation is called a synthesis operator, which gets incorporated into the design through high-level optimization passes performed by the HDL compiler. These optimizations include arithmetic optimization, resource sharing, and pin arrangement.

Arithmetic Optimization

Arithmetic optimization rearranges operators according to algebraic rules to improve circuit area and performance. For instance, the expression a + b + c + d describes a three-stage串联 addision operation. Arithmetic optimization can rearrange this to (a + b) + (c + d), reducing it to only two stages of串联 addition and making the logic faster.

Resource Sharing

Resource sharing allows multiple operations that do not overlap in time to execute on the same physical hardware. Pin rearrangement leverages the fact that certain operations (such as addition and multiplication) are not affected by swapping input ports.

Through DWBB, a given operator can be implemented using multiple hardware architectures. The synthesis tool decides which specific implementation to use based on the optimization constraints you set for your design. For example, unsigned addition can be implemented using either a ripple-carry adder architecture or a carry-lookahead adder architecture.

Library Architecture

DWBB consists of two components: a design library and a synthesis library.

• Design Library: A UNIX directory containing circuit descriptions for various parameterizable IP architectures
• Synthesis Library: A binary file with .sldb extension that links design library circuits to Synopsys synthesis tools

Circuit descriptions in the design library are stored in binary format within the synthesis library for efficient tool invocation. These circuits differ from process-dependent circuits and hard macro cells—they are parameterizable, optimizable, and fully hierarchical. The synthesis library contains information enabling synthesis tools to perform high-level optimizations, including implementation selection.

A connection hierarchy links your source code, synthesis library, and design library. First, HDL operators correlate with synthesis operators, which then bind to synthesis modules. Each synthesis module may have multiple implementation options called implementations.

Another category of IP within DWBB consists of sub-blocks. These have only one implementation and must be instantiated directly. Sub-blocks are useful for large modules that lack multiple implementations, such as error detection and correction IP.

Synthesis Operators and Modules

HDL operators are language constructs that process enput values to produce outputs. Some operators are built into the language, such as +, -, and *. User-defined subroutines (functions and procedure blocks) are also classified as HDL operators.

DWBB implements many built-in HDL operators, including +, -, *, <, >, <=, >=, /, and operations described through if and case statements. Each operator has an HDL definition that specifies the operator's behavior for simulation, along with an optional map_to_operator compiler directive that links the HDL operator to an equivalent synthesis operator. The division operator / requires a DWBB license.

Many HDL operators (including most built-in operators) map to the Synopsys standard synthesis library, standard.sldb, by default.

A synthesis library contains:

• Synthesis Operator definitions
• Synthesis Module definitions
• Binding relationships
• Declarations associating synthesis modules with implementations

Implementations themselves reside in the corresponding design library.

Synthesis Operators

Represents operations invoked by HDL operator calls. Synthesis tools automatically perform high-level optimizations such as arithmetic optimization or resource sharing.

Synthesis Modules

Define common structures for a family of implementations. All implementations of a given module share the same ports and identical input-output behavior.

Binding Relationships

Associate synthesis operators with synthesis modules. For example, a binding relationship links the synthesis operator for addition with an adder module. Multiple synthesis operators can bind to a given synthesis module, and a single operator can bind to multiple modules.

Basic Usage

1. To access synthesis libraries other than standard.sldb, you must reference these libraries through the synthetic_library and link_library variables
2. To access design libraries (except those associated with standard.sldb), use the define_design_lib command in dc_shell or configure library directory paths through the .synopsys_sim.setup file mapping mechanism
3. Use the report_synlib command to list available operators, modules, and implementations within synthesis libraries
4. To infer DWBB IP:
   • Include appropriate HDL operators in your design description
   • Analyze and elaborate your design using the analyze and elaborate commands
   • Set constraints and compile using the compile command
5. To instantiate a synthesis module:
   • Include module references in your design description
   • Analyze and elaborate
   • Set constraints and compile

Advanced Usage

1. Manually select modules and implementations by including directives in your HDL design or using the set_implementation command after reading the design into dc_shell
2. Use replace_synthetic to disable high-level optimization for synthesis operators
3. Use dont_use to disable specific synthesis modules and their implementations
4. Use set_implementation_priority to establish priority among implementations of a given module
5. By default, implementations are instantiated hierarchically. Use set_ungroup to flatten hierarchy instantiation
6. Use remove_unconnected_ports to remove unconnected ports from selected cells in your design
7. Improve synthesis library cache usage through:
   • Cache sharing
   • Populating cache with frequently used components
   • Setting synlib_optimize_non_cache_elements to false to improve compilation speed when exploring multiple design alternatives

Quick Start Configuration

Environment Setup

Add the following lines to your .synopsys_dc.setup file with a valid DesignWare license:

set synthetic_library [list dw_foundation.sldb]
set link_library [concat $target_library $synthetic_library]
set search_path [concat $search_path [list \
[format "%s%s" $synopsys_root "/dw/sim_ver"]]]
set synlib_wait_for_design_license [list "DesignWare"]

IP Access Methods

Access Buillding Block IP through operator inference, functional inference, or direct instantiation:

assign RESULT = DATA_IN1 * DATA_IN2;          // Operator Inference
assign RESULT = mult_tc(DATA_IN1, DATA_IN2);  // Function Inference
DW01_mult #(10, 12) multiplier_inst (A, B, TC, PRODUCT); // Instantiation

Synthesis Control

Design Compiler automatically selects optimal implementations for combinational DesignWare Building Block IP. Force specific implementation selection using Synopsys Compiler directives or commands:

dc_shell-t> set_dont_use standard.sldb/DW01_add/rpl
dc_shell-t> set_implementation fast_add [list add_42]

Simulation

Configure your Verilog simulator to access DWBB simulation models:

-y $SYNOPSYS/dw/sim_ver +libext+.v+

Detailed inference and instantiation documentation for VHDL and Verilog is available in the $SYNOPSYS/dw/examples directory.