IEEE Standard for Verilog Hardware Description Language

Abstract

The Verilog hradware description language (HDL) is defined in this standard. Verilog HDL serves as a formal notation intended for use throughout all phases of electronic system creation. Its dual nature as both machine-readable and human-readable enables support for hardware design development, verification, synthesis, and testing; facilitates communication of hardware design data; and aids in the maintenance, modification, and procurement of hardware components. This standard primarily targets tool implementors supporting the language and advanced language users.

Introduction

Verilog hardware description language (HDL) achieved IEEE standard status in 1995 as IEEE Std 1364-1995. The language was designed to be simple, intuitive, and effective across multiple abstraction levels using a standard textual format compatible with various design tools, including verification simulation, timing analysis, test analysis, and synthesis. These robust features have established Verilog as the preferred language for the vast majority of integrated circuit (IC) designers.

The language incorporates a comprehensive set of built-in primitives, such as logic gates, user-definable primitives, switches, and wired logic. It also supports device pin-to-pin delays and timing checks. The ability to mix abstraction levels is fundamental enabled by two primary data types: nets and variables. Continuous assignments allow expressions involving both variables and nets to drive values onto nets continuously, forming the basic structural construct. Procedural assignments enable storing calculation results (involving variable and net values) into variables, providing the basic behavioral construct. A design comprises multiple modules, each featuring an input/output (I/O) interface and a functional description that can be structural, behavioral, or a combination. These modules are organized hierarchically and interconnected through nets.

Verilog's extensibility is achieved through the programming language interface (PLI) and Verilog procedural interface (VPI) routines. These interfaces consist of collections of routines that permit external functions to access information within a Verilog HDL design description and enable dynamic interaction with simulation. Common PLI/VPI applications include integration with other simulation and computer-aided design (CAD) systems, customized debugging tools, delay calculators, and design annotators.

The language that most influenced Verilog HDL was HILO-2, developed at Brunel University in England under a contract to create a test generation system for the British Ministry of Defense. HILO-2 successfully combined gate and register transfer levels of abstraction while supporting verification simulation, timing analysis, fault simulation, and test generation.

In 1990, Cadence Design Systems made Verilog HDL publicly available, leading to the formation of the independent Open Verilog International (OVI) to manage and promote the language. In 1992, the OVI Board of Directors initiated efforts to establish Verilog HDL as an IEEE standard. The first IEEE working group was formed in 1993, and after 18 months of focused work, Verilog became an IEEE standard as IEEE Std 1364-1995.

Following standardization, the IEEE P1364 Working Group gathered feedback from global users to enhance and modify the standard, resulting in a five-year effort that produced the improved IEEE Std 1364-2001. With the completion of this standard, work continued to identify language issues and potential enhancements. As Accellera began standardizing SystemVerilog in 2001, additional concerns emerged regarding potential incompatibilities between Verilog 1364 and SystemVerilog. To address these issues, the IEEE P1364 Working Group was established as a subcommittee of the SystemVerilog P1800 Working Group, ensuring consistent resolution of compatibility challenges. The outcome of this collaborative effort is this standard, IEEE Std 1364-2005.