// NHWC to NC1HWC0 Tensor.reshape([N, H, W, C1, C0]).transpose([0, 3, 1, 2, 4])

// NCHW to NC1HWC0
Tensor.reshape([N, C1, C0, H, W]).transpose([0, 1, 3, 4, 2])

\### Fractal Data Formats Ascend processors utilize specialized fractal formats for matrix operations: 1. NZ Format (Fractal Z): - Divides matrices into (H1*W1) fractal blocks - Block storage follows column-major order (N-shaped pattern) - Internal elements use row-major (Z-shaped) ordering Conversion process: ```

// ND to NZ transformation
(..., N, H, W) ->
pad ->
(..., N, H1*H0, W1*W0) ->
reshape ->
(..., N, H1, H0, W1, W0) ->
transpose ->
(..., N, W1, H1, H0, W0)

### AI Compiler Layout Optimization AI compilers perform critical layout transformations while considering: 1. Hardware-specific requirements (e.g., CANN library for Ascend) 2. Computational graph preservation 3. Conversion overhead vs. performance gains 4. Heterogeneous computing scenarios (mobile SOCs with multiple IPs) Common transformation patterns: ```

// Pattern 1: Sequential same-format operators [NCHW] -> Op1(NCHW) -> Op2(NCHW) -> [NCHW] // No conversion needed

// Pattern 2: Mixed-format operators
[NCHW] -> CAST(NCHW->NHWC) -> Op1(NHWC) -> Op2(NHWC) -> CAST(NHWC->NCHW) -> [NCHW]

// Pattern 3: Alternating formats [NCHW] -> CAST(NCHW->NHWC) -> Op1(NHWC) -> CAST(NHWC->NCHW) -> Op2(NCHW) -> [NCHW]

Training vs. inference considerations: - Training: Optimize for operator sequences (e.g., 1x1 conv NHWC → 3x3 conv NCHW) - Inference: Handle weight layout differences across hardware platforms </div>