Synopsys IC Compiler (ICC) is an industry-standard tool for converting gate-level netlists into manufacturable layout data. The tool follows a structured workflow:

• Data Preparation: Inputs include netlists, constraint files, cell libraries, technology files, and parasitic models
• Floorplanning: Defines chip dimensions, I/O placement, macro placement, and power grid construction
• Placement: Positions standard cells and macros within the chip area
• Clock Tree Synhtesis: Builds clock distribution networks
• Routing: Connects all placed components
• Chip Finishing: Performs final optimizations including metal fill insertion

Layout Fundamentals

IC fabrication requires multiple mask layers represented by distinct layout layers. A basic inverter layout in N-well CMOS technology includes:

• N-well layer
• Active area
• N/P implant regions
• Poly gate
• Contact cuts
• Metal interconnects

Modern processes utilize multiple metal layers (6 in this experiment) for complex routing.

TCL Script Implementation

The initialization script prepares the design environment:

# Design setup configuration
set design_name "filter_design"
set lib_path "../lib/logic ../lib/milkyway"

# Library configuration
set target_lib "slow.db"
set symbol_lib "smic18.sdb"

# Create Milkyway database
create_mw_lib design_lib.mw \
    -technology ../lib/milkyway/tech/smic18_6lm.tf \
    -mw_reference_library ../lib/smic18 -open

# Import design data
import_designs "../dc/outputs/filter_post_synth.v" -format verilog -top $design_name

# Parasitic extraction setup
set_tlu_plus_files \
    -max_tluplus ../lib/milkyway/tech/tluplus/smic_max.tluplus \
    -min_tluplus ../lib/milkyway/tech/tluplus/smic_min.tluplus \
    -tech2itf_map ../lib/milkyway/tech/tluplus/tech_mapping.map

# Constraints loading
read_sdc "../dc/outputs/filter_post_synth.sdc"
set_clock_uncertainty 2 [all_clocks]

save_mw_cel
start_gui

Physical Implementation Steps

Floorplanning

Key floorplan operations:

1. Create core area with 50μm margins
2. Establish power network connections (VDD/VSS)
3. Construct power rings (METAL5/METAL6)
4. Add power straps (METAL6 vertical)

Placement

Standard cell placement with optimization:

place_opt -effort high

Clock Tree Synthesis

Clock network configuration:

• Max fanout: 30
• Routing layers: METAL1-METAL6
• Hold time fixing enabled

Routing

Interconnect implementation:

1. Set routing layer constraints (METAL1-METAL6)
2. Route clock nets first
3. Complete signal routing

Chip Finishing

Final optimizations:

• Metal-filled cell insertion
• Redundant via addition
• Design rule checking

Output Generation

Final design exports include:

• Verilog netlist (.v)
• Standard Delay Format (.sdf)
• SPEF parasitics
• GDSII stream file