1. Static Timing Analysis with PrimeTime

PrimeTime (PT) is Synopsys’ gate-level static timing sign-off solution. It exhaustively enumerates every timing path in the design, computes propagation delays, and checks setup/hold margins without requriing any functional stimulus. This is in contrast to dynamic timing simulation, which needs test vectors and can miss critical paths.

Pre-layout STA (after Design Compiler)

# pt_pre_layout.tcl
set search_path  "../../lib/logic"
set link_path    "* slow.db"

set top_design cic_filter
read_verilog "../../dc/outputs/cic_filter_post_dc.v"
current_design $top_design

set_wire_load_model -name smic18_wl10
set_wire_load_mode top

create_clock -period 156 -waveform {0 78} [get_ports clk] -name clk
create_generated_clock -divide_by 64 \
    -source [get_ports clk] [get_pins div/clk_div] -name clk_div
set_ideal_network [list clk clk_div] -no_propagate

set_clock_latency   2.5  clk
set_clock_transition  0.3  clk
set_clock_uncertainty 1.5  -setup clk
set_clock_uncertainty 0.3  -hold  clk

set_drive 0 [list clk rst_n]
set_driving_cell -lib_cell NAND2X1 in
set_load 2 [all_outputs]

set_input_delay  35 -clock clk [list in rst_n]
set_output_delay 35 -clock clk_div [all_outputs]

report_constraint -all_violators
report_timing -to [all_registers -data_pins]
report_timing -to [all_outputs]

Post-layout STA (after IC Compiler)

# pt_post_layout.tcl
set search_path  "../../lib/logic"
set link_path    "* slow.db"

set top_design cic_filter
read_verilog "../../icc/outputs/cic_filter_post_layout.v"
current_design $top_design

read_parasitics "../../icc/cic_filter.spef.max"

create_clock -period 156 -waveform {0 78} [get_ports clk] -name clk
create_generated_clock -divide_by 64 \
    -source [get_ports clk] [get_pins div/clk_div] -name clk_div
set_propagated_clock [get_clocks clk]

set_drive 0 [list clk rst_n]
set_driving_cell -lib_cell NAND2X1 in

set_input_delay  35 -clock clk [list in rst_n]
set_output_delay 35 -clock clk_div [all_outputs]
set_load 2.5 [get_ports out]

report_constraint -all_violators
report_timing -to [all_registers -data_pins]
report_timing -to [all_outputs]

Run the scripts:

cd /home/crazy/Desktop/experiment/pt/pt_pre_layout
ic
pt_shell -f pt_pre_layout.tcl

Repeat for pt_post_layout. Ensure all slack values are positive and no violations are reported.

2. Formal Equivalence Checking with Formality

Formality compares two design representations (e.g., RTL vs. gate, pre-layout vs. post-layout) to prove logical equivalence. Unlike simulation, its exhaustive and stimulus-independent.

RTL vs. Post-Synthesis Netlist

# fm_pre_layout.tcl
start_gui
set search_path "../../src ../../dc/outputs"

create_container ref
read_verilog cic_filter.v divider64.v
set_top cic_filter
set_reference_design ref:/WORK/cic_filter

create_container impl
read_verilog -netlist cic_filter_post_dc.v
read_db ../../lib/logic/slow.db
set_top cic_filter
set_implementation_design impl:/WORK/cic_filter

verify

Post-Synthesis vs. Post-Layout Netlist

# fm_post_layout.tcl
create_container ref
read_verilog -netlist ../../dc/outputs/cic_filter_post_dc.v
read_db ../../lib/logic/slow.db
set_top cic_filter
set_reference_design ref:/WORK/cic_filter

create_container impl
read_verilog -netlist ../../icc/outputs/cic_filter_post_layout.v
read_db ../../lib/logic/slow.db
set_top cic_filter
set_implementation_design impl:/WORK/cic_filter

verify

Execute:

cd /home/crazy/Desktop/experiment/fm/fm_pre_layout
ic
fm_shell -f fm_pre_layout.tcl

Repeat for fm_post_layout. Any mismatch must be resolved before proceeding.

3. Post-Layout Gate-Level Simulation

1. Create a new ModelSim project.
2. Copy the following into the working directory:
   • cic_filter_post_layout.v (gate netlist)
   • cic_filter.sdf (back-annotated timing)
   • Testbench used in RTL simulation
   • Foundry model smic18.v
3. Compile all files.
4. Start Simulation:
   • Select the testbench as top.
   • Disable optimizations (-O0).
   • Under SDF tab, add cic_filter.sdf and set Apply to Region to /testbench/cic.
   • Check Apply to Timing and Log SDF Warnings.
5. Run simulation; observe the quantized sine wave on out. Glitches caused by real interconnect delays should be visible compared to the RTL waveform.

With post-layout simulation passing, the complete digital ASIC flow is finished.