This design establishes a standardized, reusable video data interconnect interface using SystemVerilog interface constructs. It decouples timing-critical video signaling (e.g., sync pulses and pixel data) from functional blocks, enabling modular integration, scalable testbenches, and hardware-agnostic verification.

Interface Definition: video_bus_if.sv

`include "config_constants.svh"

interface video_bus_if;
  logic clk;
  logic rst_n;
  logic frame_sync;   // Frame start indicator
  logic v_blank;      // Vertical blanking signal
  logic h_blank;      // Horizontal blanking signal
  logic pixel_clk_en; // Pixel clock enable (replaces psync)
  logic [`VIDEO_DATA_WIDTH-1:0] pixel_data;

  logic is_active; // Runtime activity flag (e.g., for assertion control)
endinterface

Configuraton Header: config_constants.svh

// Global width definitions — centralized for maintainability
`define VIDEO_DATA_WIDTH 24

Top-Level Testbench: tb_video_pipeline_top.sv

`include "config_constants.svh"
`include "video_bus_if.sv"

`timescale 1ns / 1ps

module tb_video_pipeline_top;
  // Clock & reset generation
  reg sys_clk = 0;
  reg sys_rst_n = 0;

  always #5 sys_clk = ~sys_clk;
  initial begin
    sys_rst_n = 0;
    #100 sys_rst_n = 1;
  end

  // Instantiate two independent video bus interfaces
  video_bus_if src_bus();
  video_bus_if dst_bus();

  // Bind clocks and resets
  assign src_bus.clk = sys_clk;
  assign src_bus.rst_n = sys_rst_n;
  assign dst_bus.clk = sys_clk;
  assign dst_bus.rst_n = sys_rst_n;

  // DUT: Grayscale conversion unit
  video_grayscale_engine #(
    .ENABLE_SIMULATION(0),
    .PIXEL_WIDTH       (`VIDEO_DATA_WIDTH),
    .BYTE_WIDTH        (8),
    .ERROR_CODE_WIDTH  (4)
  ) dut (
    .clk_i             (sys_clk),
    .rst_n_i           (sys_rst_n),
    .src_frame_sync_i  (src_bus.frame_sync),
    .src_v_blank_i     (src_bus.v_blank),
    .src_h_blank_i     (src_bus.h_blank),
    .src_pixel_en_i    (src_bus.pixel_clk_en),
    .src_pixel_data_i  (src_bus.pixel_data),
    .dst_frame_sync_o  (dst_bus.frame_sync),
    .dst_v_blank_o     (dst_bus.v_blank),
    .dst_h_blank_o     (dst_bus.h_blank),
    .dst_pixel_en_o    (dst_bus.pixel_clk_en),
    .dst_pixel_data_o  (dst_bus.pixel_data),
    .err_code_o        ()
  );
endmodule

Design Rationale & Structure

• Modular Abstraction: The video_bus_if encapsulates all video timing and data signals as a single named entity—eliminating manual signal bundling and reducing port list clutter.
• Scalable Configuration: Widths and behavioral flags (e.g., simulation mode) are parameterized at compile time via macros or module parameters, supporting reuse across resolutions and platforms.
• Testbench Flexibility: Multiple interface instances (e.g., src_bus, dst_bus) allow independent stimulus injection and response monitoring without cross-talk.
• Verification-Ready Foundation: Reserved signals like is_active and explicit clock/reset binding simplify future integration of assertions, coverage points, and protocol checkers.

Directory Layout Convention

All non-top-level files reside in subdirectories (e.g., ./interfaces/, ./cfg/, ./dut/). The top-level testbench remains flat for visibility, while heirarchy is enforced logically—not syntactically—enabling plug-and-play composition of phases (e.g., stimulus generation, processing, analysis) without structural coupling.