Constraining Input Ports with `set_input_delay` in Static Timing Analysis

Using the set_input_delay command establishes timing constraints for paths that begin at an input port and end at a sequential element. Since the startpoint lacks a physical launch flip-flop, the constraint models an external virtual launch register clocked by a reference clock. To remove a previously applied constraint, use remove_input_delay.

set_input_delay
    delay_value port_pin_list
    [-reference_pin pin_port_name]
    [-clock clock_name]
    [-clock_fall]
    [-level_sensitive]
    [-network_latency_included]
    [-source_latency_included]
    [-rise]
    [-fall]
    [-max]
    [-min]
    [-add_delay]

Delay value and target objects
The delay_value represents the combined combinational delay from the virtual launch register to the input port. The port_pin_list argument accepts a list of ports or pins. Use braces {} or quotes to enclose multiple entries. When the target is a leaf-cell pin, the tool implicitly attaches a size_only attribute to prevent optimization during synthesis. This impilcit attribute takes precedence over an explicit set_size_only and splits the timing path.

Selecting the reference clock
The -clock option identifies the clock that drives the virtual launch register. It may point to a real clock or a virtual (source-less) clock. Almost all input delay specifications require -clock; exceptions include data-used-as-clock and propagating clock ports.

Basic example
Consider a flop with clock port clk. Create a clock first:

create_clock -period 10 [get_ports clk]

Without a constraint on input d, the setup report shows Path is unconstrained. Apply:

set_input_delay 0.5 -clock [get_clocks clk] [get_ports d]

The timing report then lists input external delay of 0.5.

Launch edge control
By default, the virtual launch register triggers on the rising edge. Use -clock_fall to model a falling-edge launch:

set_input_delay 0.6 -clock_fall -clock [get_clocks clk] [get_ports c]

Specifying a reference pin
The -reference_pin option includes the propagation delay from the reference clock origin to the given pin or port. This option cannot be combined with -network_latency_included or -source_latency_included. Example:

set_input_delay 0.7 -reference_pin [get_ports clk] -clock clk [get_ports d]
set_clock_latency 0.1 -source [get_clocks clk]

The clock network delay in the timing report now contains the source latency.

Including source and network latencies
For ideal clocks, both source and network latencies are normally included in the clock network delay. The -network_latency_included option indicates that the delay_value already accounts for network latency, so the tool avoids double-counting it. It is applicable only to ideal clocks:

set_clock_latency 0.05 [get_clocks clk]
set_input_delay 0.6 -network_latency_included -clock [get_clocks clk] [get_ports c]

-source_latency_included works similarly and applies to both ideal and propagated clocks.

Level-sensitive modeling
Append -level_sensitive to treat the virtual launch element as a latch rather then a flip-flop, enabling latch-specific timing analysis.

Edge-specific delays
Use -rise and -fall to constrain only a particular transition of the input port. Omitting both applies the delay to both edges. For example:

set_input_delay 0.8 -clock_fall -rise -clock [get_clocks clk] [get_ports c]

Max and min conditions
The -max option targets setup (maximum delay) analysis, while -min targets hold (minimum delay) analysis. When neither is given, the delay applies to both. Separate values for the same port can be specified:

set_input_delay 0.9 -max -clock_fall -rise -clock [get_clocks clk] [get_ports c]
set_input_delay 0.5 -min -clock_fall -rise -clock [get_clocks clk] [get_ports c]

Using -add_delay
Multiple set_input_delay commands referencing different clocks or edges normally overwrite earlier constraints. The -add_delay flag appends instead of replacing. It also enables automatic worst-case selection: if a newly added delay is more relaxed than an existing one, the tool retains the stricter constraint.

Scope and multicorner-multimode
The command applies only to the current scenario. When working with multiple operating corners or modes, each scenario requires its own set_input_delay constraints.

Tags: SDC set_input_delay timing constraints input delay static timing analysis

Posted on Thu, 07 May 2026 01:04:57 +0000 by daleks