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During synthesis with Design Compiler, set_drive and set_driving_cell model input port drive strength by computing transition time and additional port delay. The set_input_transition command lets you override these computed values with an explicit transition time, directly setting the port’s min_transition_fall, min_transition_rise, max_transit ...

Using the set_input_delay command establishes timing constraints for paths that begin at an input port and end at a sequential element. Since the startpoint lacks a physical launch flip-flop, the constraint models an external virtual launch register clocked by a reference clock. To remove a previously applied constraint, use remove_input_delay. ...