HDMI Protocol Overview

High-Definition Multimedia Interface (HDMI) facilitates the simultaneous transmission of uncompressed video and multi-channel audio. The standard Type-A connector features 19 pins operating at frequencies up to 160MHz, commonly found in consumer electronics. Protocol iterations (1.0, 1.3, 2.0, 2.1) progressively increase bandwidth, resolution, and refresh rate support, with version 2.0 being the prevalent standard.

Pin Configuration and Signal Routing

The interface dedicates four shielded differential pairs: three for the Red, Green, and Blue color channels, and one for the pixel clock. Additional pins support the Consumer Electronics Control (CEC) bus for device-to-device commands, the I2C bus (SCL/SDA) for reading Extended Display Identification Data (EDID), and the Hot Plug Detect (HPD) pin for connection status monitoring.

TMDS Encoding Mechanism

HDMI employs Transition Minimized Differential Signaling (TMDS) to encode parallel video and audio data into 10-bit serial streams. Video pixels undergo TMDS encoding, while audio packets utilize TERC4 encoding. Synchronization signals (HSYNC and VSYNC) are embedded exclusively within the Blue channel during control periods, while CTL0-3 signals occupy the Green and Red channels. When audio transmission is omitted, the protocol effectively operates as DVI, relying solely on TMDS and a Video Data Enable (VDE) signal to distinguish between active pixel data and control periods.

The TMDS algorithm transforms an 8-bit payload into a 10-bit encoded word:

• Bits [0:7]: Generated using XNOR or XOR operations to minimize signal transitions.
• Bit [8]: Indicates the encoding operation used (0 for XNOR, 1 for XOR).
• Bit [9]: DC balancing bit. High-speed differential receivers use AC coupling; prolonged DC bias causes decoding errors. This bit inverts the previous bits if the disparity of 1s and 0s is unbalanced, ensuring long-term DC equilibrium.

Encoder state parameters include the input data (D), control signals (C1, C0), data enable (DE), disparity counter (Cnt(t)), 1s count (N1{x}), 0s count (N0{x}), intermediate output (q_m), and final serialized output (q_out).

Video Timing Parameters

Raster displays require precise synchronization. A VSYNC pulse marks the beginning of a new frame, while an HSYNC pulse denotes the start of a new row. Due to legacy CRT electron beam retrace requirements, blanking intervals exist between active pixel regions. Horizontal Back Porch (HBP) and Horizontal Front Porch (HFP) define the delays before and after active video in a line. Similarly, Vertical Back Porch (VBP) and Vertical Front Porch (VFP) frame the active rows. These non-visible periods dictate the total pixel clock frequency required to drive a specific resolution at a target frame rate.

Xilinx 7-Series Primitives

Primitives are vendor-specific hardware macros that provide direct access to dedicated FPGA silicon features. For HDMI output, the IO Port components are critical, specifically the OSERDESE2 (Output Serializer) and OBUFDS (Differential Output Buffer). The IO block also contains delay elements (IDELAYE2/ODELAYE2, though ODELAYE2 is restricted to High-Performance banks) and logic resources for double-data-rate sampling (ODDR/IDDR via OLOGICE2/ILOGICE2).

Parallel-to-Serial Conversion (OSERDESE2)

Serializing a 10-bit TMDS word can be achieved by multiplying the clock by 10x (SDR) or 5x (DDR). The DDR approach utilizes both rising and falling edges, significantly relaxing the clock network constraints. A single OSERDESE2 primitive supports up to 8:1 serialization. To achieve 10:1, two OSERDESE2 primitives must be cascaded in a Master-Slave configuration. Due to hardware routing constraints, the slave instance must map its inputs to the D3-D8 ports, leaving D1-D2 unconnected.

OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(10),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b0),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)
) hdmi_ser_master (
    .OFB(),
    .OQ(serial_data_out),
    .SHIFTOUT1(cascade_shift1),
    .SHIFTOUT2(cascade_shift2),
    .TBYTEOUT(),
    .TFB(),
    .TQ(),
    .CLK(fast_clk_5x),
    .CLKDIV(slow_clk_1x),
    .D1(par_bit_0),
    .D2(par_bit_1),
    .D3(par_bit_2),
    .D4(par_bit_3),
    .D5(par_bit_4),
    .D6(par_bit_5),
    .D7(par_bit_6),
    .D8(par_bit_7),
    .OCE(1'b1),
    .RST(sys_reset),
    .SHIFTIN1(slave_shift1),
    .SHIFTIN2(slave_shift2),
    .T1(1'b0),
    .T2(1'b0),
    .T3(1'b0),
    .T4(1'b0),
    .TBYTEIN(1'b0),
    .TCE(1'b0)
);

Single-Ended to Differential Conversion (OBUFDS)

The serialized single-ended TMDS signal must be converted into a differential pair to comply with the HDMI electrical standard. The OBUFDS primitive handles this transformation directly at the I/O pad.

OBUFDS #(
    .IOSTANDARD("TMDS_33")
) hdmi_diff_buf (
    .O(diff_p_pin),
    .OB(diff_n_pin),
    .I(single_ended_in)
);

Hardware Interface and Reset Logic

HDMI output-only configurations can omit the Hot Plug Detect (HPD) sensing circuitry, continuously driving the TMDS lines. However, monitoring HPD is recommended to reduce unnecessary FPGA power consumption when no display is attached. Driving a 1280x720 resolution at approximately 75MHz serves as a standard baseline for verifying the video pipeline.

Asynchronous reset signals must be synchronized to the pixel clock domain before deployment. A reset synchronizer captures the asynchronous reset, releases it synchronously to the clock, and outputs an active-high reset pulse, preventing metastability and timing hazards across the design.

module reset_synchronizer (
    input  wire dest_clk,
    input  wire async_rst_n,
    output reg  synced_rst
);
    reg rst_ff1;

    always @(posedge dest_clk or negedge async_rst_n) begin
        if (!async_rst_n) begin
            rst_ff1   <= 1'b1;
            synced_rst <= 1'b1;
        end else begin
            rst_ff1   <= 1'b0;
            synced_rst <= rst_ff1;
        end
    end
endmodule