Digital circuit design employs two fundamental modeling approaches: bottom-up and top-down methodologies. Contemporary design practices typically combine both strategies.

Design Methodologies

The top-down approach begins with defining the overall architecture at the system level, then progressively decomposing into smaller functional blocks. Conversely, the bottom-up methodology starts with basic building blocks and constructs more complex structures by combining them.

In practical implementations, designers adopt a hybrid strategy. The architectural definition establishes the top-level module, while logic designers partition the complete design into submodules based on functionality. Simultaneously, circuit designers optimize lower-level modules and utilize them to construct higher-level representations. Both streams proceed in opposing directions until converging at an intermediate design point.

Four Abstracsion Levels for Module Description

Verilog supports multiple abstraction perspectives for describing identical hardware functionality:

1. Behavioral level: Describes functionality algorithmically
2. Dataflow level: Defines circuit operation through continuous assignments
3. Structural level: Interconnects pre-defined components
4. Physical level: Represents actual gate-level implemantation

Simulation Components

Digital circuit simulation comprises two distinct elements:

• Design Under Test (DUT): The hardware description being verified
• Testbench: Stimulus generation module that exercises the DUT

Two primary smiulation approaches exist:

1. Interactive simulation: Manual stimulus application through simulator commands
2. Automated simulation: Self-contained testbenches that automatically generate and apply stimuli

Hierarchical Counter Design Example

This section demonstrates hierarchical modeling through a four-bit ripple counter implementation using falling-edge triggered toggle flip-flops.

Top-Level Counter Module

The counter connects four toggle flip-flops in a cascading configuration:

module sync_binary_counter (
    input  wire        clock,
    input  wire        reset_n,
    output wire [3:0]  count_out
);

    toggle_flipflop tff_0 (
        .clk    (clock),
        .rst_n  (reset_n),
        .q      (count_out[0])
    );
    
    toggle_flipflop tff_1 (
        .clk    (count_out[0]),
        .rst_n  (reset_n),
        .q      (count_out[1])
    );
    
    toggle_flipflop tff_2 (
        .clk    (count_out[1]),
        .rst_n  (reset_n),
        .q      (count_out[2])
    );
    
    toggle_flipflop tff_3 (
        .clk    (count_out[2]),
        .rst_n  (reset_n),
        .q      (count_out[3])
    );

endmodule

Toggle Flip-Flop Implementation

The toggle flip-flop combines a data flip-flop with an inverter to achieve toggle functionality:

module toggle_flipflop (
    input  wire clk,
    input  wire rst_n,
    output wire q
);
    
    wire data_in;
    
    data_flipflop dff_inst (
        .clk    (clk),
        .rst_n  (rst_n),
        .d      (data_in),
        .q      (q)
    );
    
    not gate_inv (data_in, q);

endmodule

Fundamental Data Flip-Flop

The base-level component implements edge-triggered storage behavior:

module data_flipflop (
    input  wire clk,
    input  wire rst_n,
    input  wire d,
    output reg  q
);
    
    always @(negedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= 1'b0;
        else
            q <= d;
    end

endmodule

Testbench Module

The verification environment instantiates the counter and applies stimulus sequences:

`timescale 1ns/1ps
module counter_verification;
    reg         clock;
    reg         reset_n;
    wire [3:0]  count_out;
    
    sync_binary_counter dut (
        .clock      (clock),
        .reset_n    (reset_n),
        .count_out  (count_out)
    );
    
    initial begin
        clock = 0;
    end
    always #5 clock = ~clock;
    
    initial begin
        reset_n = 1'b0;
        #15
        reset_n = 1'b1;
        #180
        reset_n = 1'b0;
        #10
        reset_n = 1'b1;
        #20
        $finish;
    end
    
    initial begin
        $monitor($time, "\tcounter = %d", count_out);
    end

endmodule

Module Versus Instance Distinction

Understanding the distinction between module definitions and their instances proves essential in Verilog. A module serves as a template describing circuit functionality, while an instance represents a specific usage of that template within the design. Each instance maintains its own distinct set of signals, enabling multiple instantiations of identical module types within a single design. This separation between template and instantiation enables scalable and reusable hardware descriptions.