Finite State Machine Fundamentals

A Finite State Machine (FSM) is a deterministic behavioral model used to coordinate sequential operations, manage control signals, and enforce predefined transition rules within digital systems. At its core, an FSM consists of a finite set of states, input conditions, and output actions. Based on how outputs are derived, FSMs are classified into two primary architectures: Moore and Mealy machines.

In a Moore machine, outputs depend exclusively on the current registered state. Output transitions occur strictly on active clock edges, ensuring that signals remain stable throughout the clock period. Conversely, a Mealy machine generates outputs based on a combination of the current state and immediate input values. This allows Mealy models to react within the same clock cycle, but it also introduces combinatorial dependencies that can affect timing and stability.

Architectural Divergence: Timing, State Density, and Reliability

The choice between Moore and Mealy implementations hinges on several critical design factors:

• State Count & Resource Utilization: Mealy architectures typically require fewer states because output logic is embedded directly into transition conditions. For instance, a sequence detector might need three states in a Moore design but only two in a Mealy equivalent, as output asesrtion is tied to input edges rather than dedicated state entries.
• Response Latency: Mealy machines exhibit faster reaction times. Output signals change asynchronously as soon as relevant inputs toggle, often yielding a detection flag one clock cycle earlier than Moore machines, which must wait for the state register to update.
• Glitch Immunity & Safety: Moore outputs are fully registered, making them inherently glitch-free and highly predictable when cascaded with downstream logic. Mealy outputs are combinatorial; rapid input changes near clock edges can generate transient spikes (glitches). When multiple FSMs are interconnected, unregistered Mealy outputs risk creating asynchronous feedback loops or metastability issues.
• Decoding Complexity: Moore machines may require additional decoding logic to map internal state vectors to external control signals, introducing extra gate delays after the clock edge. Mealy machines bypass this by computing outputs directly from transition logic, though at the cost of timing predictability.

Implementation Methodologies in Verilog

Historically, FSMs were implemented using a three-process methodology: one sequential block for state registration, one combinatorial block for next-state logic, and a third block (combinatorial or sequential) for output generation. While structurally explicit, this approach can complicate timing closure and synthesis optimization.

Modern design practices favor a synchronous two-block approach. The first block handles state registration and transition conditions. The second block (or multiple independent blocks) generates outputs using registered logic. This eliminates combinatorial output hazards, simplifies static timing analysis, and aligns with contemporary FPGA/ASIC synthesis algorithms that automatically infer FSMs from well-structured code.

Moore Architecture: Synchronous Output Generation

The following example implements a non-overlapping sequence detector for the pattern 101. Outputs are strictly synchronized with the clock, guaranteeing stable control signals.

module moore_seq_detect (
    input  wire         clk,
    input  wire         rst_n,
    input  wire         data_in,
    output reg          match_out
);
    // State encoding (one-hot for decoding efficiency)
    localparam [3:0]
        ST_IDLE  = 4'b0001,
        ST_A     = 4'b0010,
        ST_B     = 4'b0100,
        ST_C     = 4'b1000;

    reg [3:0] state_reg, state_nxt;

    // Process 1: Synchronous state register
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            state_reg <= ST_IDLE;
        else
            state_reg <= state_nxt;
    end

    // Process 2: Combinatorial next-state logic
    always @(*) begin
        state_nxt = state_reg;
        case (state_reg)
            ST_IDLE: state_nxt = (data_in) ? ST_A : ST_IDLE;
            ST_A:    state_nxt = (data_in) ? ST_A : ST_B;
            ST_B:    state_nxt = (data_in) ? ST_C : ST_IDLE;
            ST_C:    state_nxt = ST_IDLE;
            default: state_nxt = ST_IDLE;
        endcase
    end

    // Process 3: Registered output assignment
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            match_out <= 1'b0;
        else
            match_out <= (state_reg == ST_C);
    end
endmodule

Mealy Arcihtecture: Reactive Output Generation

Mealy machines evaluate inputs and states simultaneously. The detector below identifies the same 101 pattern but asserts the output combinatorially upon meeting transition criteria, reducing state count and latency.

module mealy_seq_detect (
    input  wire         clk,
    input  wire         rst_n,
    input  wire         data_in,
    output reg          match_out
);
    localparam [2:0]
        ST_S0 = 3'b001,
        ST_S1 = 3'b010,
        ST_S2 = 3'b100;

    reg [2:0] state_reg, state_nxt;

    // Process 1: State registration
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) state_reg <= ST_S0;
        else        state_reg <= state_nxt;
    end

    // Process 2: Next-state & transition logic
    always @(*) begin
        state_nxt = state_reg;
        case (state_reg)
            ST_S0: state_nxt = (data_in) ? ST_S1 : ST_S0;
            ST_S1: state_nxt = (data_in) ? ST_S1 : ST_S2;
            ST_S2: state_nxt = (data_in) ? ST_S1 : ST_S0;
            default: state_nxt = ST_S0;
        endcase
    end

    // Process 3: Combinatorial output logic (Mealy characteristic)
    always @(*) begin
        if (!rst_n) match_out = 1'b0;
        else        match_out = (state_reg == ST_S2 && data_in);
    end
endmodule

Design Trade-offs and Verification Strategies

Selecting between Moore and Mealy topologies requires evaluating system constraints. Moore machines are preferred in safety-critical or high-noise environments where output stability and glitch immunity are paramount. Their registered outputs also simplify formal verification and timing constraints. Mealy machines excel in low-latency applications and resource-constrained designs, where minimizing flip-flops and reducing state depth directly impacts power and area metrics.

Verification methodologies differ accordingly. Moore outputs can be sampled synchronously in testbenches, aligning cleanly with clock edges. Mealy outputs require careful stimulus alignment and race-condition checks, as output assertions may occur asynchronously relative to the clock. Modern simulation environments typically employ clocked sampling with delayed evaluation windows to capture Mealy transitions accurately without introducing artificial timing violations.