Verilog Preprocessor Directives and IEEE Standards

According to IEEE standards, these directives are used to mark modules as cell modules, indicating they contain cell definitions. Some PLI routines utilize cell modules for applications like delay calculation. These directives can appear any where in the source code, but placing them outside module definitions is recommended. Practical usage examples remain to be explored.

`default_nettype Directive

This directive specifies the net type for implicit nets - those connections not explicitly declared. When default\_nettype is not specified or when resetall is encountered, the default net type is wire. Setting `default_nettype to none requires explicit declaration of all nets; failure to do so results in compilation errors.

`define Macro Definition

Format: ``define MACRO_NAME macro_content`

This directive performs text substitution during preprocessing, replacing all occurrences of the macro name with the specified content throughout the subsequent code. Macros help simplify code by replacing lengthy strings with short identifiers or giving meaningful names to numeric constants. Modifying macro definitions enables large-scale code changes efficiently.

Macro Usage Guidelines:

  • Use uppercase names to distinguish macros from variables
  • Macros can be defined inside or outside modules, with scope extending from definition point to file end
  • Reference macros using the backtick prefix: ``MACRO_NAME`
  • Macro substitution performs simple text replacement without syntax checking
  • No semicolon needed after macro definitions - including one incorporates it into substitution
  • Macro definitions support nesting, allowing new macros to reference previously defined ones
  • Macro names and content must appear on the same line; comments within content are not substituted

`undef Directive

This directive removes previously defined macro definitions from the compilation scope.

Conditional Compilation

The directives ifdef`, elsif, ``else, endif`, and ifndef enable conditional compilation. ``ifndef includes code when a flag is undefined, while ``endif` terminates conditional blocks.

`ifdef FLAG_A
// Code block A
`elsif FLAG_B  
// Code block B
`elsif FLAG_C
// Code block C
`else
// Default code block
`endif

`include File Inclusion

Format: ``include "filename"`

This directive copies the entire content of the specified file into the current file at the inclusion point. This mechanism facilitates code reuse by allowinng common macro definitions, tasks, and module declarations to be shared across multiple files. While module instantiation by name is typically preferred for modular design, file inclusion remains useful for sharing utility code and definitions.

`timescale Time Scale

Format: ``timescale time_unit / time_precision`

Valid values include 1, 10, 100 with units: s, ms, us, ns, ps, fs. Time precision determines the minimum timing resolution during simulation, affecting how fractional delays are handled.

`resetall Directive

This directive resets all compiler directives to their default values. Placing ``resetall` at the beginning of source files is recommended. Using this directive inside module declarations or UDP definitions is invalid.

unconnected\_drive and nounconnected_drive

These directives control handling of unconnected ports with in their scope:

`unconnected_drive pull1  // Pull up unconnected ports
// ... code section
`nounconnected_drive      // End special handling

Use pull1 for pull-up or pull0 for pull-down configuration.

Tags: Verilog preprocessor Macros ConditionalCompilation FileInclusion

Posted on Mon, 13 Jul 2026 16:41:10 +0000 by mindspin311