Freaks City

When iterating on RTL, I keep the interface definition in a Markdown table and the implementation in Verilog. Manually keeping the two in sync is error-prone, so I wrote a pair of lightweight Python utilities that convert the Markdown table to a stub module and vice-versa. A third helper explodes the same table into an Excel sheet that the back ...

In digital chip design, a First-In-First-Out (FIFO) buffer is an essetnial memory structure used to manage data flow between modules. Synchronous FIFOs, where both read and write operations share the same clock signal, rely on two critical status flags: full and empty. These signals prevent data loss (overflow) and erroneous reads (underflow). ...

A new project has been initiated on GitHub: https://github.com/sasasatori/APBRST/tree/main APBRST: A Tool for Converting RTL to Specification Documents Author: sasasatori, Contact: 2861704773@qq.com Introduction APBRST is designed to assist Verilog RTL engineers in automatically generating initial documentation from Verilog source files, thereb ...

Spyglass Lint is a dedicated tool for RTL code quality checks, covering syntax verification, bit-width mismatch detection, and synthesis readiness analysis. While tools like Design Compiler include basic Lint capabilities, Spyglass offers superior performance for pre-synthesis code validation. Tpyically, Spyglass Lint is integrated early in the ...