A new project has been initiated on GitHub: https://github.com/sasasatori/APBRST/tree/main
APBRST: A Tool for Converting RTL to Specification Documents
Author: sasasatori, Contact: 2861704773@qq.com
Introduction
APBRST is designed to assist Verilog RTL engineers in automatically generating initial documentation from Verilog source files, thereby accelerating comprehension and documentation tasks. Future enhancements may include SystemVerilog support and reverse engineering of RTL from specifications. This tool leverages Pyverilog, a Python-based parser for Verilog.
License
Licensed under Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
Installation Requirements
The following dependencies are required:
- Python3: version 3.7 or higher
- Icarus Verilog: version 10.1 or higher
sudo apt install iverilog
- Jinja2: version 2.10 or higher
- PLY: version 3.4 or higher
pip3 install jinja2 ply
After installing Pyverilog via setup.py, APBRST can be used directly:
python3 setup.py install
Usage
Run APBRST directly using Python:
python3 verilog2spec.py ./verilog/<filename>.v
Example Verilog files are located in the /verilog directory, such as cmsdk_ahb_gpio.v and fifo.v
Sample output for cmsdk_ahb_gpio.v:
User@System:~/<path>/APBRST$ python3 verilog2spec.py ./verilog/cmsdk_ahb_gpio.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
-------------------------generate module tree-------------------------
cmsdk_ahb_gpio (top)
├── u_ahb_to_gpio: cmsdk_ahb_to_iop
└── u_iop_gpio: cmsdk_iop_gpio
-------------------------generate param table-------------------------
| Parameter | Default Value | Function |
| :-------------------: | :-----------: | :------: |
| ALTERNATE_FUNC_MASK | 16'h0000 | |
| ALTERNATE_FUNC_DEFAULT| 16'h0000 | |
| BE | 0 | |
-------------------------generate port table-------------------------
| Port | Width | Direction | Function |
| :----------: | :---: | :-------: | :------: |
| HCLK | 1 | Input | |
| HRESETn | 1 | Input | |
| FCLK | 1 | Input | |
| HSEL | 1 | Input | |
| HREADY | 1 | Input | |
| HTRANS | 2 | Input | |
| HSIZE | 3 | Input | |
| HWRITE | 1 | Input | |
| HADDR | 12 | Input | |
| HWDATA | 32 | Input | |
| ECOREVNUM | 4 | Input | |
| PORTIN | 16 | Input | |
| HREADYOUT | 1 | Output | |
| HRESP | 1 | Output | |
| HRDATA | 32 | Output | |
| PORTOUT | 16 | Output | |
| PORTEN | 16 | Output | |
| PORTFUNC | 16 | Output | |
| GPIOINT | 16 | Output | |
| COMBINT | 1 | Output | |
Sample output for fifo.v:
User@System:~/<path>/APBRST$ python3 verilog2spec.py ./verilog/fifo.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
-------------------------generate module tree-------------------------
fifo (top)
-------------------------generate param table-------------------------
| Parameter | Default Value | Function |
| :-------: | :-----------: | :------: |
-------------------------generate port table-------------------------
| Port | Width | Direction | Function |
| :----------: | :---: | :-------: | :------: |
| clk | 1 | Input | |
| srst | 1 | Input | |
| wr_en | 1 | Input | |
| rd_en | 1 | Input | |
| din | 32 | Input | |
| dout | 32 | Output | |
| empty | 1 | Output | |
| full | 1 | Output | |
Roadmap
- Module hierarchy extraction
- Paramter table generation
- Port list compilation
- Detection of repeated instances via
generate for(;;) endgenerate - Comment parsing and extraction
- Multi-file processing
- SystemVerilog compatibility
- Specification-to-RTL generation