Module Interface Overview

The AXI4 Master interface consists of five distinct channels: Write Address (AW), Write Data (W), Write Response (B), Read Address (AR), and Read Data (R). Signals prefixed with M_AXI_ indicate the Master side of the interface. Specifically, AR_* signals belong to the Read Address channel, AW_* to the Write Address channel, R_* to the Read Data channel, W_* to the Write Data channel, and B_* to the Write Response channel. Identifying the channel requires looking beyond the prefix; for instance, while ARESETN starts with "AR", it is actually the global active-low reset signal.

Utility Functions for Bit Width Calculation

To handle dynamic address widths, the design typically employs a logarithmic function to calculate the necessary bit width for a given depth. The following function determines the minimum number of bits required to represent an integer value.

function automatic integer get_addr_width(input integer depth);
    integer width;
    begin
        for (width = 0; depth > 0; width = width + 1)
            depth = depth >> 1;
        get_addr_width = width;
    end
endfunction

Signal Initialization and Synchronization

Internal signals are typically named in lowercase to distinguish them from the uppercase port signals defined in the module header. A criticla aspect of the master logic is generating a clean initiation pulse. The following logic uses a two-stage flip-flop chain to synchronize the INIT_AXI_TXN input and create a single-cycle pulse txn_start_pulse.

reg init_req_d1, init_req_d2;
wire txn_start_pulse;

always @(posedge M_AXI_ACLK) begin
    if (!M_AXI_ARESETN) begin
        init_req_d1 <= 1'b0;
        init_req_d2 <= 1'b0;
    end else begin
        init_req_d1 <= INIT_AXI_TXN;
        init_req_d2 <= init_req_d1;
    end
end

assign txn_start_pulse = init_req_d1 & ~init_req_d2;

Write Address Channel Logic

The Write Address channel manages the transmission of the address and control information. The axi_awvalid signal is asserted when a write operation is requested and de-asserted upon successful handshake with the slave, indicated by M_AXI_AWREADY.

reg aw_valid_reg;

always @(posedge M_AXI_ACLK) begin
    if (!M_AXI_ARESETN || txn_start_pulse) begin
        aw_valid_reg <= 1'b0;
    end else if (start_wr_txn) begin
        aw_valid_reg <= 1'b1;
    end else if (M_AXI_AWREADY && aw_valid_reg) begin
        aw_valid_reg <= 1'b0;
    end
end

Write Data and Response Handling

The Write Data channel operates similarly, with axi_wvalid following the control logic. The M_AXI_WSTRB signal indicates which byte lanes contain valid data. Once the data is transferred, the Master waits for the Write Response on the B channel. The axi_bready signal must be asserted to accept the response from the slave.

Read Address and Data Channels

For read operations, the Read Address channel uses axi_arvalid to signal a valid address. The Read Data channel utilizes axi_rready to accept data from the slave. Error detection is handled by monitoring the M_AXI_RRESP signal.

System Functionality and Address Generation

Unlike a Slave interface, the Master must actively generate addresses and manage the data flow. The write address increments by a fixed offset (e.g., 4 bytes) after every successful handshake.

reg [31:0] axi_awaddr;

always @(posedge M_AXI_ACLK) begin
    if (!M_AXI_ARESETN || txn_start_pulse) begin
        axi_awaddr <= 32'h0;
    end else if (M_AXI_AWREADY && aw_valid_reg) begin
        axi_awaddr <= axi_awaddr + 32'h00000004;
    end
end

State Machine Design

A Finite State Machine (FSM) orchestrates the transaction sequence. The typical states include:

• IDLE: Initializes all registers and waits for a transaction trigger.
• INIT_WRITE: Manages the write address and data phases.
• INIT_READ: Manages the read address phase.
• DATA_COMPARE: Verifies the read data against expected values and flags errors.

Transaction Completion and Verification

Counter signals track the progress of transactions. last_write and last_read signals indicate the completion of data bursts. Logic checks writes_done and reads_done to ensure that the number of completed handshakes matches the expected transaction length.

Error handling mechanisms compare the data read back (M_AXI_RDATA) with an expected value. A mismatch sets an error flag, and the M_AXI_BRESP or M_AXI_RRESP signals are checked to ensure no slave-side errors occurred during the transfer.