VL26: Sequence Detection with Don't-Care Conditions

Building upon the previous problem, this challenge becomes straightforward. For those unfamiliar, refer to my earlier post on 牛客数字IC刷题记录（1）—序列检测器VL25 for fuondational knowledge.

This problem modifies the earlier version slightly and can be solved using two distinct approaches:

Key changes are ennotated with comments labeled "change" within the code.

1. State Machine Approach:

`timescale 1ns/1ns
module sequence_detector(
    input clk,
    input rst_n,
    input data_in,
    output reg found_match
);

    parameter STATE_IDLE     = 10'b00_0000_0001,
              STATE_A        = 10'b00_0000_0010,
              STATE_B        = 10'b00_0000_0100,
              STATE_C        = 10'b00_0000_1000,
              STATE_D        = 10'b00_0001_0000,
              STATE_E        = 10'b00_0010_0000,
              STATE_F        = 10'b00_0100_0000,
              STATE_G        = 10'b00_1000_0000,
              STATE_H        = 10'b01_0000_0000,
              STATE_I        = 10'b10_0000_0000; //change1: Increased bit width from 8 to 9 bits

    reg [9:0] current_state, next_state;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            current_state <= STATE_IDLE;
        else
            current_state <= next_state;
    end

    always @(*) begin
        if (!rst_n)
            next_state <= STATE_IDLE;
        else
            case (current_state) //change2: Simplified transitions involving don't care states
                STATE_IDLE:  next_state <= data_in ? STATE_B : STATE_IDLE; // 0
                STATE_A:     next_state <= data_in ? STATE_C : STATE_IDLE; // 1
                STATE_B:     next_state <= data_in ? STATE_C : STATE_IDLE; // 1
                STATE_C:     next_state <= STATE_D; // x
                STATE_D:     next_state <= STATE_E; // x
                STATE_E:     next_state <= STATE_F; // x
                STATE_F:     next_state <= data_in ? STATE_G : STATE_IDLE; // 1
                STATE_G:     next_state <= data_in ? STATE_H : STATE_IDLE; // 1
                STATE_H:     next_state <= ~data_in ? STATE_I : STATE_IDLE; // 0
                STATE_I:     next_state <= STATE_IDLE;
                default:     next_state <= STATE_IDLE;
            endcase
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            found_match <= 1'b0;
        else if (current_state == STATE_I) //change3: Match achieved at final state
            found_match <= 1'b1;
        else
            found_match <= 1'b0;
    end

endmodule

2. Shift Register Comparison Method

In contrast to the fixed pattern of 01110001 from the previous example, this version introduces several don't-care conditions. To address this, we extract only the significant bits and compare them against the expected sequence:

`timescale 1ns/1ns
module sequence_detector(
    input clk,
    input rst_n,
    input data_in,
    output reg found_match
);

    reg [8:0] shift_register; //change1: Adjusted register size from 8 to 9 bits
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            shift_register <= 9'b0;
        else
            shift_register <= {shift_register[7:0], data_in}; //change2: Updated bit width
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            found_match <= 1'b0;
        else if ((shift_register[8:6] == 3'b011) && (shift_register[2:0] == 3'b110)) //change3: Extract key bits for comparison
            found_match <= 1'b1;
        else
            found_match <= 1'b0;
    end

endmodule

Both methods effectively solve the problem.