The shift-and-add method performs multiplication by iterating over the bits of the multiplicand. Starting from the least significant bit, if the bits 1, the multiplier is shifted left by the bit position and accumulated; if 0, no addition is performed. This process repeats for all bits.

Example: a = 101, b = 101, product = 25.

• Bit 0 of b = 1 → add a << 0
• Bit 1 of b = 0 → no addition
• Bit 2 of b = 1 → add a << 2

Below is an 8-bit multiplier using a finite state machine (FSM) with three states. The design uses a counter to track bit processing and shifts the multiplier left while shifting the multiplicand right each cycle.

// Shift-add multiplier: 8-bit inputs, 16-bit result
module mult_shift_add (
    input         clk,
    input         rst_n,
    input  [7:0]  multiplicand,  // y
    input  [7:0]  multiplier,    // x
    output reg [15:0] product
);

    reg [7:0]  cnt;
    reg [15:0] mult_reg;   // holds shifted multiplier
    reg [7:0]  mnd_reg;    // holds multiplicand
    reg [15:0] acc;        // accumulator
    reg [1:0]  state;

    localparam IDLE = 2'b00,
               CALC = 2'b01,
               DONE = 2'b10;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            product  <= 0;
            cnt      <= 0;
            mult_reg <= 0;
            mnd_reg  <= 0;
            acc      <= 0;
            state    <= IDLE;
        end else begin
            case (state)
                IDLE: begin
                    mult_reg <= {8'd0, multiplier};
                    mnd_reg  <= multiplicand;
                    acc      <= 0;
                    cnt      <= 0;
                    state    <= CALC;
                end
                CALC: begin
                    if (cnt == 8) begin
                        state <= DONE;
                    end else begin
                        if (mnd_reg[0]) begin
                            acc <= acc + mult_reg;
                        end
                        mult_reg <= mult_reg << 1;
                        mnd_reg  <= mnd_reg >> 1;
                        cnt      <= cnt + 1;
                    end
                end
                DONE: begin
                    product <= acc;
                    state   <= IDLE;
                end
                default: state <= IDLE;
            endcase
        end
    end
endmodule

Testbench example:

`timescale 1ns/1ps
module tb_mult_shift_add;
    reg         clk, rst_n;
    reg  [7:0]  a, b;
    wire [15:0] p;

    mult_shift_add uut (
        .clk         (clk),
        .rst_n       (rst_n),
        .multiplicand(b),
        .multiplier  (a),
        .product     (p)
    );

    initial clk = 0;
    always #10 clk = ~clk;

    initial begin
        #1  rst_n = 0;
        #21 rst_n = 1;
        #21 a = 4; b = 5;          // 4*5 = 20
        #200;
        a = 22; b = 30;            // 22*30 = 660
        #200;
        $finish;
    end
endmodule

The shift-and-add multiplier uses minimal logic but requires multiple clock cycles per product. It is suitable for low-speed signal processing where hardware area is critical.