Verilog is a hardware descriptino language (HDL) primarily used to model digital and mixed-signal systems. Unlike high-level programming languages such as C, Verilog describes hardware behavior and structure, making it essential for FPGA and ASIC design workflows.

Core Language Constructs

Every Verilog design begins with a module declaration, which defines the interface and internal logic of a hardware block. The module name should typically match the filename. It ends with endmodule, forming a self-contained unit. Signal declarations define how data flows in and out of the module: - input: signals entering the module - output: signals leaving the module - inout: bidirectional signals (less common in basic designs) Internally, signals are typed as either: - wire: represents physical connections; driven by continuous assignments or gate outputs - reg: holds values over time; used in procedural blocks like always### Behavioral and Structural Modeling

Two primary constructs drive logic implementation: - assign: used for continuous assignments (combinational logic) - always: describes sequential or combinational behavior triggered by sensitivity lists These enable modeling everything from simple multiplexers to complex state machines. ### Example: 2-to-1 Multiplexer

module mux2to1(y, d0, d1, sel);
    input d0, d1, sel;
    output y;
    reg y;

    always @(*) begin
        if (sel == 1'b0)
            y = d0;
        else
            y = d1;
    end
endmodule

This module selects between d0 and d1 based on the sel signal. The @(*) sensitivity list automatically infers all relevant inputs. ### Testbench Basics

Verification in Verilog uses testbenches—non-synthesizable modules that generate stimuli and monitor responses. Testbenches leverage system tasks like $display and timing controls (#delay) not available in synthesizable code. Example testbench snippet: ``` module tb; reg sig_a; reg [1:0] vec_b; reg [5:0] vec_c;

initial begin
    sig_a = 1'b1;
    vec_b = 2'b00;
    vec_c = 6'b101001;

    $display("Concatenation 1: %b", {sig_a, vec_b});      // Outputs: 100
    $display("Concatenation 2: %b", {vec_c[5:3], sig_a}); // Outputs: 1011
    $display("Replication: %b", {4{sig_a}});             // Outputs: 1111
end

endmodule

Here, concatenation `{...}` and replication `{n{signal}}` demonstrate powerful bit manipulation features useful in verification. Testbenches do not map to physical hardware but are critical for functional validation before synthesis.